 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 19-0858; Rev 0; 7/07 High-Power, Quad, PSE Controller for Power-Over-Ethernet General Description The MAX5952 is a quad -48V power controller designed for use in IEEETM 802.3af-compliant/pre-IEEE 802.3at-compatible power-sourcing equipment (PSE). This device provides powered device (PD) discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard. The MAX5952 is pin compatible with MAX5945/ LTC4258/LTC4259A PSE controllers and provides additional features. The MAX5952 features high-power mode that provides up to 45W per port. The MAX5952 provides instantaneous readout of each port current through the I2C interface. The MAX5952 also provides high-capacitance detection for legacy PDs. The device features an I2C-compatible, 3-wire serial interface, and is fully software configurable and programmable. The class-overcurrent detection function enables system power management to detect if a PD draws more than the allowable current. The MAX5952's extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. The MAX5952 provides four operating modes to suit different system requirements. Auto mode allows the device to operate automatically without any software supervision. Semi-automatic mode automatically detects and classifies a device connected to a port after initial software activation, but does not power up that port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. The MAX5952 provides input undervoltage lockout (UVLO), input undervoltage detection, a load-stability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage slewrate limit during startup, power-good status, and fault status. The MAX5952's programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5952 is available in a 36-pin SSOP package and is rated for both extended (-40C to +85C) and upper commercial (0C to +85C) temperature ranges. Features IEEE 802.3af Compliant/Pre-IEEE 802.3at Compatible Instantaneous Readout of Port Current Through I2C Interface High-Power Mode Enables Up to 45W Per Port High-Capacitance Detection for Legacy Devices Pin Compatible to MAX5945 and LTC4258/LTC4259A Four Independent Power-Switch Controllers PD Detection and Classification Load-Stability Safety Check During Detection Supports Both DC and AC Load Removal Detections I2C-Compatible, 3-Wire Serial Interface Current Foldback and Duty-Cycle-Controlled Current Limit Open-Drain INT Signal Direct Fast Shutdown Control Capability MAX5952 Ordering Information PART MAX5952AEAX+* MAX5952AUAX+ MAX5952CEAX+* MAX5952CUAX+* TEMP RANGE -40C to +85C 0C to +85C -40C to +85C 0C to +85C PINPACKAGE 36 SSOP 36 SSOP 36 SSOP 36 SSOP PKG CODE A36-4 A36-4 A36-4 A36-4 +Denotes a lead-free package. *Future product--contact factory for availability. Applications Power-Sourcing Equipment (PSE) Switches/Routers Midspan Power Injectors IEEE is a trademark of the Institute of Electrical and Electronics Engineers, Inc. ________________________________________________________________ Maxim Integrated Products 1 Pin Configuration and Selector Guide appear at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VEE, unless otherwise noted.) AGND, DGND, DET_, VDD, RESET, A3-A0, SHD_, OSC, SCL, SDAIN, and AUTO ......................................-0.3V to +80V OUT_........................................................-12V to (AGND + 0.3V) GATE_ (internally clamped) (Note 1) ..................-0.3V to +11.4V SENSE_ ..................................................................-0.3V to +24V VDD, RESET, MIDSPAN, A3-A0, SHD_, OSC, SCL, SDAIN and AUTO to DGND ..................................-0.3V to +7V INT and SDAOUT to DGND....................................-0.3V to +12V AGND to DGND........................................................-0.3V to +7V Maximum Current into INT, SDAOUT, DET_ .......................80mA Maximum Power Dissipation (TA = +70C) 36-Pin SSOP (derate 11.4mW/C above +70C) ..........941mW Operating Temperature Ranges: MAX5952_EAX............................................-40C to +85C MAX5952_UAX ....................................................0C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C Note 1: GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEE may damage the device. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER POWER SUPPLIES VAGND Operating Voltage Range VDGND VDD VDD to VDGND, VDGND = VAGND VDD to VDGND, VDGND = VEE VOUT_ = VEE, VSENSE_ = VEE, DET_ = AGND, all logic inputs open, SCL = SDAIN = VDD. INT and SDAOUT open. Measured at AGND in power mode after GATE_ pullup All logic inputs high, measured at VDD Power mode, gate drive on, VGATE = VEE SHD_ = DGND, VGATE_ = VEE + 10V VSENSE = 600mV, VGATE_ = VEE + 2V VGATE - VEE, power mode, gate drive on 9 -40 30 VAGND - VEE 32 0 1.71 3.0 60 60 5.50 5.5 V SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Currents IEE 4.8 6.8 mA IDIG GATE DRIVER AND CLAMPING GATE_ Pullup Current Weak GATE_ Pulldown Current Maximum Pulldown Current External Gate Drive IPU IPDW IPDS VGS 3.0 -50 42 70 10 5.6 -60 55 11 A A mA V 2 _______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER CURRENT LIMIT IVEE = 00 Maximum VSENSE_ allowed during current limit, VOUT_ = 0V (ICUT = 000) (Note 3) IVEE = 01 IVEE = 10 IVEE = 11 ICUT = 000 (Class 0/3) ICUT =110 (Class 1) Overcurrent Threshold After Startup Overcurrent VSENSE_ threshold allowed for t tFAULT after startup; VOUT_ = 0V, (IVEE = 00) ICUT = 111 (Class 2) ICUT = 001 ICUT = 010 ICUT = 011 ICUT = 100 ICUT =101 ICUT = 000, ICUT = 110, ICUT = 111 ICUT = 001...101 202 192 186 170 177 47 86 265 310 355 398 443 212 202 190 180 186 55 94 280 327 374 419 466 28 V 10 220 212 mV 200 190 196 62 101 mV 295 345 395 440 488 SYMBOL CONDITIONS MIN TYP MAX UNITS MAX5952 Current-Limit Clamp Voltage VSU_LIM VFLT_LIM Foldback Initial OUT_ Voltage VFLBK_ST VOUT_ - VEE, above which the current-limit trip voltage starts folding back, IVEE = 00 Foldback Final OUT_ Voltage Minimum Foldback Current-Limit Threshold SENSE_ Input Bias Current IVEE = 00, ICUT = 000, VOUT - VEE above VFLBK_END which the current-limit trip voltage reaches VTH_FB VTH_FB VOUT_ = AGND = 60V, IVEE = 00, ICUT = 000 VSENSE_ = VEE -2 50 V 64 +2 mV A _______________________________________________________________________________________ 3 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER SUPPLY MONITORS VEE Undervoltage Lockout VEE Undervoltage Lockout Hysteresis VEE Overvoltage Lockout VEE Overvoltage Lockout Hysteresis VEE Undervoltage VEEUVLO VEEUVLOH VEE_OV VOVH VEE_UV VEE_UV event bit is set if AGND - VEE < VEE_UV, VEE increasing VDD_OV event bit is set if VDD - VDGND > VDD_OV; VDD increasing VDD_OV is set if VDD - VDGND > VDD_UV, VDD decreasing MAX5952A MAX5952C MAX5952A MAX5952C AGND - VEE, AGND - VEE increasing Ports shut down if AGND - VEE < VUVLO VEEUVLOH VEE_OV event bit sets and ports shut down if AGND - VEE > VEE_OV, AGND increasing 28.5 3 62.5 1 40 3.82 V 5.7 2.7 V 4.2 2 120 Ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing (Note 4) Thermal hysteresis, temperature decreasing (Note 5) VOUT = AGND, all modes OUT_ discharge current, detection and classification off, port shutdown, VOUT_ = AGND - 2.8V VOUT_ - VEE, OUT_ decreasing Minimum time PGOOD has to be high to set bit in register 10h 200 1.5 2.0 220 3 V mV V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Overvoltage VDD_OV VDD Undervoltage VDD_UV VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis Thermal Shutdown Threshold VDDUVLO VDDHYS Device operates when VDD - DGND > VDDUVLO, VDD increasing TSHD 150 C Thermal Shutdown Hysteresis OUTPUT MONITOR OUT_ Input Current Idle Pullup Current at OUT_ PGOOD High Threshold PGOOD Hysteresis PGOOD Low-to-High Glitch Filter TSHDH 20 C IBOUT IDIS PGTH PGHYS tPGOOD 2 260 2.5 A A V mV ms 4 _______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER LOAD DISCONNECT DC Load Disconnect Threshold AC Load Disconnect Threshold (Note 6) Oscillator Buffer Gain OSC Fail Threshold (Note 7) OSC Input Impedance Load Disconnect Timer DETECTION Detection Probe Voltage (First Phase) Detection Probe Voltage (Second Phase) Current-Limit Protection Short-Circuit Threshold Open-Circuit Threshold Resistor Detection Window Resistor Rejection Window CLASSIFICATION Classification Probe Voltage Current-Limit Protection VCL ICILIM VAGND - VDET_ during classification DET_ = AGND, during classification, measure current through DET_ Class 0, Class 1 Classification Current Thresholds ICL Classification current thresholds between classes Class 1, Class 2 Class 2, Class 3 Class 3, Class 4 Class 4, Class 5 16 68 5.5 13 21 31 45 6.5 14.5 23 33 48 20 81 7.5 16 25 35 51 mA V mA VDPH1 VDPH2 IDLIM VDCP ID_OPEN RDOK RDBAD AGND - VDET_ during the first detection phase AGND - VDET_ during the second detection phase VDET_ = AGND, during detection, measure current through DET_ If AGND - VOUT < VDCP after the first detection phase a short circuit to AGND is detected First point measurement current threshold for open condition (Note 9) Detection rejects lower values Detection rejects higher values 32 19.0 3.8 9.0 1.5 4 9.3 1.75 1 12.5 26.5 15.2 4.2 9.6 2.0 V V mA V A k k VDCTH IACTH AOSC VOSC_FAIL ZOSC tDISC Minimum VSENSE allowed before disconnect (DC disconnect active), VOUT_ = 0V Current into DET_, for I < IACTH the port powers off, ACD_EN_ bit = H; VOSC_IN = 2.2V VDET_ / VOSC, ACD_EN_ bit = H Port does not power on if VOSC < VOSC_FAIL and ACD_EN_ bit is high OSC input impedance when all the ACD_EN_ are active Time from VSENSE < VDCTH to gate shutdown (Note 8) 2.5 300 2.9 1.8 100 300 400 3.75 320 3.0 5.0 350 3.1 2.2 mV A V/V V k ms SYMBOL CONDITIONS MIN TYP MAX UNITS MAX5952 _______________________________________________________________________________________ 5 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER Digital Input Low Digital Input High Internal Input Pullup/Pulldown Resistor Open-Drain Output Low Voltage Digital Input Leakage Open-Drain Leakage TIMING Startup Time tSTART Time during which a current limit set by VSU_LIM is allowed, starts when the GATE_ is turned on (Note 5) Maximum allowed time for an overcurrent condition set by VFLT_LIM after startup (Note 5) Minimum delay between any port turning off, does not apply in case of a reset Time allowed for the port voltage to reset before detection starts tDET tDMID tCLASS tDLY Time allowed for classification Time VAGND must be above the VEEUVLO thresholds before the device operates RSTR bits = 00 Time a port has to wait before turning on after an overcurrent fault, RSTR_EN_ bits = high RSTR bits = 01 RSTR bits = 10 RSTR bits = 11 Watchdog Clock Period ADC PERFORMANCE Resolution Range LSB Step Size Integral Nonlinearity (Relative) INL 9 0.51 1 0.5 Bits V mV LSB tWD Rate of decrement of the watchdog timer 2 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 164 ms ms Maximum time allowed before detection is completed 2.0 19 50 60 70 ms SYMBOL VIL VIH RDIN VOL IDL IOL Pullup (pulldown) resistor to VDD (DGND) to set default level ISINK = 15mA Input connected to the pull voltage Open-drain high impedance, VO = 3.3V 2.4 25 50 75 0.4 2 2 CONDITIONS MIN TYP MAX 0.9 UNITS V V k V A A DIGITAL INPUTS/OUTPUTS (Referred to DGND) Fault Time Port Turn-Off Time Detection Reset Time Detection Time Midspan Mode Detection Delay Classification Time VEEUVLO Turn-On Delay tFAULT tOFF 50 60 0.5 80 70 ms ms 90 330 2.4 23 4 ms ms s ms ms Restart Timer tRESTART 6 _______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER Differential Nonlinearity SYMBOL DNL VSENSE = 100mV ADC Absolute Accuracy VSENSE = 250mV VSENSE = 400mV TIMING CHARACTERISTICS (For 2-Wire Fast Mode, Note 10) Serial-Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time for a START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data in Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tSU, STO CB tSP 1.2 0.6 1.2 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 150 400 kHz s s s s s ns ns ns ns s pF ns 5A (90) EF (239) 183 (387) CONDITIONS MIN TYP 0.1 61 (97) F8 (248) 190 (400) 67 (103) 101 (257) 19F (415) Hex (Dec) MAX UNITS LSB MAX5952 Limits to -40C are guaranteed by design. Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register Map and Description section). Note 4: Functional test is performed over thermal shutdown entering test mode. Note 5: Default values. The startup and fault times can be also programmed through the I2C serial interface (see the Register Map and Description section). Note 6: This is the default value. Threshold can be programmed through serial interface R23h[2:0]. Note 7: AC disconnect works only if (VDD - VDGND) 3V and DGND is connected to AGND. Note 8: tDISC can also be programmed through the serial interface (R16H) (see the Register Map and Description section). Note 9: RD = (VOUT_2 - VOUT_1) / (IDET_2 - IDET_1). VOUT_1, VOUT_2, IDET_2 and IDET_1 represent the voltage at OUT_ and the current at DET_ during phase 1 and 2 of the detection. Note 10: Guaranteed by design. Not subject to production testing. Note 2: Note 3: _______________________________________________________________________________________ 7 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Characteristics (VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.) ANALOG SUPPLY CURRENT vs. INPUT VOLTAGE 5.2 5.1 SUPPLY CURRENT (mA) 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 32 37 42 47 52 57 62 INPUT VOLTAGE (V) MEASURED AT AGND MAX5952 toc01 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX5952 toc02 DIGITAL SUPPLY CURRENT vs. TEMPERATURE 4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 MAX5952 toc03 5.3 5.3 5.2 5.1 SUPPLY CURRENT (mA) 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 -40 -15 10 35 60 5.0 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C) DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX5952 toc04 VEE UNDERVOLTAGE LOCKOUT vs. TEMPERATURE MAX5952 toc05 GATE OVERDRIVE vs. INPUT VOLTAGE 9.48 9.46 9.44 9.42 9.40 9.38 9.36 9.34 9.32 9.30 9.28 9.26 9.24 9.22 9.20 32 37 42 47 52 57 INPUT VOLTAGE (V) MAX5952 toc06 6 MEASURED AT VDD 5 SUPPLY CURRENT (mA) 4 3 2 1 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 30.0 29.5 29.0 28.5 28.0 27.5 27.0 UNDERVOLTAGE LOCKOUT (V) 5.0 -40 -15 10 35 60 85 GATE OVERDRIVE (V) 62 SUPPLY VOLTAGE (V) TEMPERATURE (C) GATE OVERDRIVE vs. TEMPERATURE MAX5952 toc07 SENSE TRIP VOLTAGE vs. TEMPERATURE MAX5952 toc08 SENSE TRIP VOLTAGE vs. INPUT VOLTAGE 189 SENSE TRIP VOLTAGE (mV) 188 187 186 185 184 183 182 181 MAX5952 toc09 11.0 10.5 GATE OVERDRIVE (V) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 -40 -15 10 35 60 200 195 SENSE TRIP VOLTAGE (mV) 190 185 180 175 170 190 85 180 -40 -15 10 35 60 85 32 37 42 47 52 57 62 TEMPERATURE (C) INPUT VOLTAGE (V) TEMPERATURE (C) 8 _______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.) FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE MAX5952 toc10 FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE MAX5952 toc10a DC LOAD DISCONNECT THRESHOLD vs. TEMPERATURE DC LOAD DISCONNECT THRESHOLD (mV) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60 85 MAX5952 toc11 300 250 VSENSE - VEE (mV) 200 150 100 50 0 0 10 20 30 40 350 300 VSENSE - VEE (mV) 250 200 150 100 50 0 5.0 50 0 10 20 30 40 50 VOUT - VEE (V) VOUT - VEE (V) TEMPERATURE (C) OVERCURRENT TIMEOUT (RLOAD = 240 TO 57) MAX5952 toc12 OVERCURRENT RESPONSE WAVEFORM (MAX5952AUAX) (RLOAD = 240 TO 57) (AGND - VOUT) 50V/div 0V IOUT 200mA/div 0A VGATE_ 10V/div VEE INT 5V/div 0A VEE 0V 400s/div GATE 10V/div INT 2V/div MAX5952 toc13 (AGND - VOUT) 50V/div 0V IOUT 200mA/div 0V 20ms/div SHORT-CIRCUIT RESPONSE TIME MAX5952 toc14 SHORT-CIRCUIT RESPONSE TIME MAX5952 toc15 (AGND - VOUT) 20V/div 0V (AGND - VOUT) 20V/div 0V 0A IOUT 200mA/div IOUT 10A/div 130mA VGATE_ 10V/div VEE 4s/div VEE 20ms/div VGATE_ 10V/div _______________________________________________________________________________________ 9 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.) RESET TO OUT TURN-OFF DELAY MAX5952 toc16 ZERO-CURRENT DETECTION WAVEFORM MAX5952 toc17 RESET 2V/div 0V (AGND - VOUT) 20V/div 0V IOUT 200mA/div 0A VGATE_ 10V/div VEE INT 2V/div 0V 100ms/div IOUT 200mA/div 0A VGATE_ 5V/div VEE 100s/div OVERCURRENT RESTART DELAY MAX5952 toc18 STARTUP WITH VALID PD (25k AND 0.1F) MAX5952 toc19 (AGND - VOUT) 20V/div 0V IOUT 200mA/div 0A 0A VGATE_ 10V/div VEE 400ms/div 0V (AGND - VOUT) 20V/div IOUT 100mA/div VGATE_ 5V/div VEE 100ms/div DETECTION WITH INVALID PD (25k AND 10F) MAX5952 toc20 DETECTION WITH INVALID PD (15k) MAX5952 toc21 (AGND - VOUT) 20V/div 0V (AGND - VOUT) 5V/div 0V IOUT 1mA/div 0A IOUT 1mA/div 40ms/div 100ms/div 10 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.) STARTUP IN MIDSPAN MODE WITH VALID PD (25k AND 0.1F) MAX5952 toc23 DETECTION WITH INVALID PD (33k) MAX5952 toc22 (AGND - VOUT) 5V/div 0V 0V (AGND - VOUT) 20V/div IOUT 100mA/div IOUT 1mA/div 0A VGATE_ 5V/div VEE 100ms/div 100ms/div 0A DETECTION WITH MIDSPAN MODE WITH INVALID PD (15k) MAX5952 toc24 DETECTION WITH MIDSPAN MODE WITH INVALID PD (33k) MAX5952 toc25 (AGND - VOUT) 5V/div 0V (AGND - VOUT) 5V/div 0V 0A IOUT 1mA/div VGATE_ 10V/div 400ms/div 0A IOUT 1mA/div VGATE_ 10V/div 400ms/div VEE VEE DETECTION WITH OUTPUT SHORTED MAX5952 toc26 DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 1) MAX5952 toc27 0V (AGND - VOUT) 5V/div 0V (AGND - VOUT) 5V/div IOUT 1mA/div 0A 0A IOUT 1mA/div VEE 40ms/div VGATE_ 10V/div VEE VGATE_ 10V/div 40ms/div ______________________________________________________________________________________ 11 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.) DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 2) MAX5952 toc28 STARTUP WITH DIFFERENT PD CLASSES MAX5952 toc29 0V (AGND - VOUT) 5V/div (AGND - VOUT) 5V/div 0A IOUT 1mA/div CLASS 5 CLASS 4 CLASS 3 CLASS 2 CLASS 1 40ms/div IOUT 20mA/div VEE VGATE_ 10V/div 40ms/div Pin Description PIN 1 NAME RESET FUNCTION Hardware Reset. Pull RESET low for at least 300s to reset the device. All internal registers reset to their default value. The address (A0-A3), and AUTO and MIDSPAN input-logic levels latch on during low-tohigh transition of RESET. RESET is internally pulled up to VDD with a 50k resistor. Midspan Mode Input. An internal 50k pulldown resistor to DGND sets the default mode to end-point PSE operation (power-over-signal pairs). Pull MIDSPAN to VDIG to set midspan operation. The MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section). Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition using software or by pulling RESET low (see the Interrupt section for more information about interrupt management). Serial Interface Clock Line Input Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Operating Circuits). Connect SDAOUT to SDAIN if using a 2-wire, I2C-compatible system. Serial Interface Input Data Line. Connect the data line optocoupler output to SDAIN (see the Typical Operating Circuits). Connect SDAIN to SDAOUT if using a 2-wire, I2C-compatible system. 2 MIDSPAN 3 4 5 6 INT SCL SDAOUT SDAIN 12 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Pin Description (continued) PIN 7-10 NAME A3-A0 FUNCTION Address Bits. A3-A0 form the lower part of the device's address. Address inputs default high with an internal 50k pullup resistor to VDD. The address values latch when VDD or VEE ramps up and exceeds its UVLO threshold or after a reset. The 3 MSBs of the address are set to 010. Detection/Classification Voltage Outputs. Use DET1 to set the detection and classification probe voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect scheme (see the Typical Operating Circuits). Digital Ground. Connect to digital ground. Positive Digital Supply. Connect to a digital power supply (reference to DGND). Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD with a 50k resistor. Analog Ground. Connect to the high-side analog supply. MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and connect a current-sense resistor between SENSE_ and VEE (see the Typical Operating Circuits). MAX5952 11-14 15 16 17- 20 21 22, 25, 29, 32 DET1-DET4 DGND VDD SHD1-SHD4 AGND SENSE4, SENSE3, SENSE2, SENSE1 GATE4, GATE3, GATE2, GATE1 23, 26, 30, 33 Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external MOSFET (see the Typical Operating Circuits). 24, 27, 31, 34 28 MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor OUT4, OUT3, (100 to 100k). The low leakage at OUT_ limits the drop across the resistor to less than 100mV (see the OUT2, OUT1 Typical Operating Circuits). VEE Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1F capacitor between AGND and VEE. Auto or Shutdown Mode Input. Force AUTO high to enter auto mode after a reset or power-up. Drive low to put the MAX5952 into shutdown mode. In shutdown mode, software controls the operational modes of the MAX5952. A 50k internal pulldown resistor defaults to AUTO low. AUTO latches when VDD or VEE ramps up and exceeds its UVLO threshold or when the device resets. Software commands can take the MAX5952 out of AUTO while AUTO is high. Oscillator Input. AC-disconnect detection function uses OSC. Connect a 100Hz 10%, 2VP-P 5%, +1.2V offset sine wave to OSC. If the oscillator positive peak falls below the OSC_FAIL threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power-up. When not using the ACdisconnect detection function, leave OSC unconnected. 35 AUTO 36 OSC ______________________________________________________________________________________ 13 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Functional Diagram VDD SCL SDAIN SDAOUT SHD_ OSC_IN DGND CURRENT SENSING SERIAL PORT INTERFACE (SPI) A0 DETECTION/ CLASSIFICATION SM PORT STATE MACHINE (SM) ACD_ENABLE 50A A=3 GATE_ AUTO PWR_EN MIDSPAN CENTRAL LOGIC UNIT (CLU) RESET REGISTER FILE DGND VDD AC DISCONNECT SIGNAL (ACD) 13V CLAMP AC DETECTION 9-BIT ADC CONVERTER 10V A2 REGISTER FILE A3 VOLTAGE SENSING OUT_ OSCILLATOR MONITOR VOLTAGE PROBING AND CURRENT-LIMIT CONTROL DET_ A1 FAST DISCHARGE CONTROL 100mA 90A MAX INT ACD REFERENCE CURRENT SENSE_ CURRENT MEASUREMENT 9 BITS ADC CURRENT LIMIT (ILIM) CURRENT-LIMIT DETECTOR AGND ANALOG BIAS/ SUPPLY MONITOR +10V ANALOG +5V DIG VOLTAGE REFERENCES CURRENT REFERENCES VEE OPEN CIRCUIT (OC) OVERCURRENT (OVC) FOLDBACK CONTROL MAX5952 4mV 182mV 212mV 14 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Detailed Description The MAX5952 is a quad -48V power controller designed for use in IEEE 802.3af-compliant/pre-IEEE 802.3at-compatible PSE. This device provides PD discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard. The MAX5952 is pin compatible with the MAX5945/LTC4258/LTC4259A PSE controllers and provides additional features. The MAX5952 features a high-power mode which provides up to 45W per port. The device allows the user to program the current-limit and overcurrent thresholds up to 2.5 times the default thresholds. The MAX5952 can also be programmed to decrease the current-limit and overcurrent threshold by 15% for high operating voltage conditions to keep the output power constant. The MAX5952 provides instantaneous readout of each port current through the I2C interface. The MAX5952 also provides high-capacitance detection for legacy PDs. The MAX5952 is fully software configurable and programmable through an I2C-compatible, 3-wire serial interface with 49 registers. The class-overcurrent detection function enables system power management to detect if a PD draws more than the allowable current. The MAX5952's extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. The MAX5952 provides four operating modes to suit different system requirements. Auto mode allows the device to operate automatically without any software supervision. Semi-auto mode automatically detects and classifies a device connected to a port after initial software activation but does not power up that port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. The MAX5952 provides input undervoltage lockout, input undervoltage detection, a load-stability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage slew-rate limit during startup, power-good, and fault status. The MAX5952's programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5952 communicates with the system microcontroller through an I 2C-compatible interface. The MAX5952 features separate input and output data lines (SDAIN and SDAOUT) for use with optocoupler isolation. As a slave device, the MAX5952 includes four address inputs allowing 16 unique addresses. A separate INT output and four independent shutdown inputs (SHD_) provide fast response from a fault to port shutdown between the MAX5952 and the microcontroller. A RESET input allows hardware reset of the device. Reset Reset is a condition the MAX5952 enters after any of the following conditions: 1) After power-up (V EE and V DD rise above their UVLO thresholds). 2) Hardware reset. The RESET input is driven low and back high again any time after power-up. 3) Software reset. Writing a 1 into R1Ah[4] any time after power-up. 4) Thermal shutdown. During a reset, the MAX5952 resets its register map to the reset state as shown in Table 37 and latches in the state of AUTO (pin 35) and MIDSPAN (pin 2). During normal operation, change at the AUTO and MIDSPAN input is ignored. While the condition that caused the reset persists (i.e. high temperature, RESET input low, or UVLO conditions) the MAX5952 does not acknowledge any addressing from the serial interface. Port Reset (R1Ah [3:0]) Set high anytime during normal operation to turn off power and clear the events and status registers of the corresponding port. Port reset only resets the events and status registers. Midspan Mode In midspan mode, the device adopts cadence timing during the detection phase. When cadence timing is enabled and a failed detection occurs, the port waits between 2s and 2.4s before attempting to detect again. Midspan mode is activated by setting R11[1] high. The status of the MIDSPAN pin is written to R11[1] during power-up or after a reset. MIDSPAN is internally pulled low by a 50k resistor. ______________________________________________________________________________________ 15 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Operation Modes The MAX5952 contains four independent, but identical state machines to provide reliable and real-time control of the four network ports. Each state machine has four operating modes: auto mode, semi-auto mode, manual, and shutdown. Auto mode allows the device to operate automatically without any software supervision. Semiauto mode, upon request, continuously detects and classifies a device connected to a port but does not power up that port until instructed by software. Manual mode allows total software control of the device and is useful in system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. Switching between auto, semi, or manual mode does not interfere with the operation of the port. When the port is set into shutdown mode, all the port operations are immediately stopped and the port remains idle until shutdown is exited. Automatic (Auto) Mode Enter automatic (auto) mode by forcing the AUTO input high prior to a reset, or by setting R12h[P_M1,P_M0] to [1,1] during normal operation (see Tables 16 and 16a). In auto mode, the MAX5952 performs detection, classification, and powers up the port automatically once a valid PD is detected at the port. If a valid PD is not connected at the port, the MAX5952 repeats the detection routine continuously until a valid PD is connected. Going into auto mode, the DET_EN and CLASS_EN bits are set to high and stay high unless changed by software. Using software to set DET_EN and/or CLASS_EN low causes the MAX5952 to skip detection and/or classification. As a protection, disabling the detection routine in auto mode does not allow the corresponding port to power up, unless the DET_BY (R23H[4]) is set to 1. The AUTO status is latched into the register only during a reset. Any changes to the AUTO input after reset are ignored. Semi-Automatic (Semi-Auto) Mode Enter semi-auto mode by setting R12h[P_M1,P_M0] to [1,0] during normal operation (see Tables 16 and 16a). In semi-auto mode, the MAX5952, upon request, performs detection and/or classification repeatedly but does not power up the port(s), regardless of the status of the port connection. Setting R19h[PWR_ON_] (Table 22) high immediately terminates detection/classification routines and turns on power to the port(s). R14h[DET_EN_, CLASS_EN_] default to low in semi-auto mode. Use software to set R14h[DET_EN_, CLASS_EN_] to high to start the detection and/or classification routines. R14h[DET_EN_, CLASS_EN_] are reset every time the software commands a power off of the port (either through reset or PWR_OFF). In any other case, the status of the bits is left unchanged (including when the state machine turns off the power because a load disconnect or a fault condition is encountered). Manual Mode Enter manual mode by setting R12h[P_M1,P_M0] to [0,1] during normal operation (see Tables 16 and 16a). Manual mode allows the software to dictate any sequence of operation. Write a 1 to both R14h[DET_EN_] and R14h[CLASS_EN_] to start detection and classification operations, respectively, and in that priority order. After execution, the command is cleared from the register(s). PWR_ON_ has highest priority. Setting PWR_ON_ high at any time causes the device to immediately enter the powered mode. Setting DET_EN and CLASS_EN high at the same time causes detection to be performed first. Once in the powered state, the device ignores DET_EN_ or CLASS_EN_ commands. When switching to manual mode from another mode, DET_EN_, CLASS_EN_ default to low. These bits become pushbutton rather than configuration bits (i.e., writing ones to these bits while in manual mode commands the device to execute one cycle of detection and/or classification. The bits are reset back to zeros at the end of the execution). Shutdown Mode Enter shutdown mode by forcing the AUTO input low prior to a reset, or by setting R12h[P_M1,P_M0] to [0,0] during normal operation (see Tables 16 and 16a). Putting the MAX5952 into shutdown mode immediately turns off power and halts all operations to the corresponding port. The event and status bits of the affected port(s) are also cleared. In shutdown mode, the DET_EN, CLASS_EN and PWR_ON commands are ignored. In shutdown mode, the serial interface operates normally. PD Detection When PD detection is activated, the MAX5952 probes the output for a valid PD. After each detection cycle, the device sets the DET_END_ bit R04h/05h[3:0] high and reports the detection results in the status registers R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The DET_END_ bit is reset to low when read through R05h or after a port reset. 16 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet A valid PD has a 25k discovery signature characteristic as specified in the IEEE 802.3af/at standard. Table 1 shows the IEEE 802.3af/at specification for a PSE detecting a valid PD signature. See the Typical Operating Circuits and Figure 1 (Detection, Classification, and Power-Up Port Sequence). The MAX5952 can probe and categorize different types of devices connected to the port such as: a valid PD, an open circuit, a low resistive load, a high resistive load, a high capacitive load, a positive DC supply, or a negative DC supply. During detection, the MAX5952 keeps the external MOSFET off and forces two probe voltages through the DET_ input. The current through the DET_ input is measured as well as the voltage at OUT_. A two-point slope measurement is used as specified by the IEEE 802.3af standard to verify the device connected to the port. The MAX5952 implements appropriate settling times and a 100ms digital integration to reject 50Hz/60Hz powerline noise coupling. An external diode, in series with the DET_ input, restricts PD detection to the first quadrant as specified by the IEEE 802.3af/at standard. To prevent damage to non-PD devices, and to protect itself from an output short circuit, the MAX5952 limits the current into DET_ to less than 2mA maximum during PD detection. In midspan mode, the MAX5952 waits 2.2s before attempting another detection cycle after every failed detection. The first detection, however, happens immediately after issuing the detection command. High-Capacitance Detection The CLC_EN bit in register R23h[5] enables the large capacitor detection feature for legacy PD devices. When CLC_EN = 1, the high-capacitance detection limit is extended up to 100F. CLC_EN = 0 is the default condition for the normal capacitor size detection. See Table 1 and the Register Map and Description section. MAX5952 Table 1. PSE PI Detection Modes Electrical Requirement (Table 33-2 of the IEEE 802.3af Standard) PARAMETER Open-Circuit Voltage Short-Circuit Current Valid Test Voltage Voltage Difference Between Test Points Time Between Any Two Test Points Slew Rate Accept Signature Resistance Reject Signature Resistance Open-Circuit Resistance Accept Signature Capacitance Reject Signature Capacitance Signature Offset Voltage Tolerance Signature Offset Current Tolerance SYMBOL VOC ISC VVALID VTEST tBP VSLEW RGOOD RBAD ROPEN CGOOD CBAD VOS IOS 19 < 15 500 -- 10 0 0 MIN -- -- 2.8 1 2 MAX 30 5 10 -- -- 0.1 26.5 > 33 -- 150 -- 2.0 12 UNITS V mA V V ms V/s k k k nF F V A This timing implies a 500Hz maximum probing frequency ADDITIONAL INFORMATION In detection mode only In detection mode only ______________________________________________________________________________________ 17 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Powered Device Classification (PD Classification) During the PD classification mode, the MAX5952 forces a probe voltage (-18V) at DET_ and measures the current into DET_. The measured current determines the class of the PD. After each classification cycle, the device sets the CL_END_ bit (R04h/05h[7:4]) high and reports the classification results in the status registers R0Ch[6:4], R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit is reset to low when read through register R05h or after a port reset. Both status registers, R04h, and R05h are cleared after the port powers down. Table 2 shows the IEEE 802.3af requirement for a PSE classifying a PD at the power interface (PI). The MAX5952 supports high power beyond the IEEE 802.3af standard by providing additional classifications (Class 5 and ping-pong classification). If these conditions are met, the MAX5952 enters startup where it turns on power to the port. An internal signal, POK_, asserts high when VOUT is within 2V from VEE. PGOOD_ status bits are set high if POK_ stays high longer than tPGOOD. PGOOD immediately resets when POK goes low. The PWR_CHG bit sets when a port powers up or down. PWR_EN sets when a port powers up and resets when a port shuts down. The port shutdown timer lasts 0.5ms and prevents other ports from turning off during that period, except in the case of emergency shutdowns (RESET = L, RESET_IC = H, VEEUVLO, VDDUVLO, and TSHD). The MAX5952 always checks the status of all ports before turning off. A priority logic system determines the order to prevent the simultaneous turn-on or turn-off of the ports. The port with the lesser ordinal number gets priority over the others (i.e., port 1 turns on first, port 2 second, port 3 third and port 4 fourth). Setting PWR_OFF_ high turns off power to the corresponding port. Powered State When the MAX5952 enters a powered state, the tSTART and tDISC timers are reset. Before turning on the port power, the MAX5952 checks if any other port is not turning on and if the t FAULT timer is zero. Another check is performed if the ACD_EN bit is set, in this case the OSC_FAIL bit must be low (oscillator is okay) for the port to be powered. 80ms 0V 150ms tDETI 150ms tDETII 21.3ms tCLASS t 0V Table 2. PSE Classification of a PD (Table 33.4 of the IEEE 802.3af) MEASURED ICLASS (mA) 0 to 5 > 5 and < 8 8 to 13 > 13 and < 16 16 to 21 > 21 and < 25 25 to 31 > 31 and < 35 35 to 45 > 45 and < 51 51 to 68 CLASSIFICATION Class 0 May be Class 0 and 1 Class 1 May be Class 1 or 2 Class 2 May be Class 2 or 3 Class 3 May be Class 3 or 4 Class 4 May be Class 4 or 5 Class 5 -4V -9V OUT_ -18V -48V Figure 1. Detection, Classification, and Power-Up Port Sequence 18 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet is programmable through the ICUT registers R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], R2Bh[2:0], and the IVEE bits in register R29h[1:0]. See the High-Power Mode section for more information on the ICUT register. After power-off due to an overcurrent fault, and if the RSTR_EN bit is set, the tFAULT timer is not immediately reset but starts decrementing at the same slower pace. The MAX5952 allows the port to be powered on only when the tFAULT counter is at zero. This feature sets an automatic duty-cycle protection to the external MOSFET avoiding overheating. The MAX5952 continuously flags when the current exceeds the maximum current allowed for the class as indicated in the CLASS status register. When class overcurrent occurs, the MAX5952 sets the IVC bit in register R09h. MAX5952 POK tPGOOD PGOOD ICUT Register and High-Power Mode Figure 2. PGOOD Timing Overcurrent Protection A sense resistor RS connected between SENSE_ and VEE monitors the load current. Under normal operating conditions, the voltage across RS (VRS) never exceeds the threshold V SU_LIM. If V RS exceeds V SU_LIM, an internal current-limiting circuit regulates the GATE voltage, limiting the current to ILIM = VSU_LIM / RS. During transient conditions, if VRS exceeds VSU_LIM by more than 1V, a fast pulldown circuit activates to quickly recover from the current overshoot. During startup, if the current-limit condition persists, when the startup timer, t START, times out, the port shuts off, and the STRT_FLT_ bit is set. In the normal powered state, the MAX5952 checks for overcurrent conditions as determined by VFLT_LIM = ~88% of VSU_LIM. The tFAULT counter sets the maximum allowed continuous overcurrent period. The tFAULT counter increases when VRS exceeds VFLT_LIM and decreases at a slower pace when VRS drops below VFLT_LIM. A slower decrement for the tFAULT counter allows for detecting repeated short-duration overcurrents. When the counter reaches the tFAULT limit, the MAX5952 powers off the port and asserts the IMAX_FLT_ bit. For a continuous overstress, a fault latches exactly after a period of tFAULT. VSU_LIM ICUT Register The ICUT register determines the maximum current limits allowed for each port of the MAX5952. The 3 ICUT bits (R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], and R2Bh[2:0]) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE standard limit (see Tables 34a, 34b, and 34c). The ICUT registers can be written to directly through the I 2 C interface when CL_DISC (R17h[2]) is set to 0 (see Table 3). In this case, the current limit of the port is configured regardless of the status of the classification. By setting the CL_DISC bit to 1, the MAX5952 automatically sets the ICUT register based upon the classification result of the port. See Table 3 and the Register Map and Description section. Table 3. Automatic ICUT Programming CL_DISC 0 1 1 1 PORT CLASSIFICATION RESULT Any 1 2 0, 3 RESULTING ICUT REGISTER BITS User programmed ICUT = 110 ICUT = 111 ICUT = 000 ______________________________________________________________________________________ 19 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 High-Power Mode When CL_DISC (R17h[2]) is set to 0, high-power mode is configured by setting the ICUT bits to any combination other than 000, 110, or 111 (note that 000 is the default value for the IEEE standard limit). See Table 3 and the Register Map and Description section. current source pulls down GATE_ to VEE to turn off the MOSFET. The pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. Use the following equation to set the maximum slew rate: VOUT IGATE = t CGD where CGD is the total capacitance between GATE and DRAIN of the external MOSFET. Current limit and the capacitive load at the drain control the slew rate during startup. During current-limit regulation, the MAX5952 manipulates the GATE_ voltage to control the voltage at SENSE_ (VRS). A fast pulldown activates if VRS overshoots the limit threshold (VSU_LIM). The fast pulldown current increases with the amount of overshoot. The maximum fast pulldown current is 100mA. During turn-off, when the GATE voltage reaches a value lower than 1.2V, a strong pulldown switch is activated to keep the MOSFET securely off. Foldback Current During startup and normal operation, an internal circuit senses the voltage at OUT_ and reduces the currentlimit value when (VOUT_ - VEE) > 28V. The foldback function helps to reduce the power dissipation on the FET. The current limit eventually reduces to 1/3 of ILIM when (VOUT_ - VEE ) > 48V (see Figure 3a). For highpower mode, the foldback starts when (VOUT_ - VEE ) > 10V (see Figure 3b). In high-power mode, the current limit (ILIM) is reduced up to 1/8 of its programmed value when (VOUT_ - VEE ) > 48V. MOSFET Gate Driver Connect the gate of the external n-channel MOSFET to GATE_. An internal 50A current source pulls GATE_ to (VEE + 10V) to turn on the MOSFET. An internal 40A (VSENSE_ - VEE) VSU_LIM (VRS - VEE) VSU_LIM VSU_LIM / 3 VSU_LIM / 3 28V 48V (VOUT_ - VEE) 10V 48V (VOUT_ - VEE) Figure 3a. Foldback Current Characteristics Figure 3b. Foldback Current Characteristics for High-Power Mode 20 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Digital Logic VDD supplies power for the internal logic circuitry. VDD ranges from +3.0V to +5.5V and determines the logic thresholds for the CMOS connections (SDAIN, SDAOUT, SCL, AUTO, SHD_, A_). This voltage range enables the MAX5952 to interface with a nonisolated low-voltage microcontroller. The MAX5952 checks the digital supply for compatibility with the internal logic. The MAX5952 also features a VDD undervoltage lockout (VDDUVLO) of +2.0V. A VDDUVLO condition keeps the MAX5952 in reset and the ports shut off. Bit 0 in the supply event register shows the status of VDDUVLO (Table 12) after VDD has recovered. All logic inputs and outputs reference to DGND. DGND and AGND must be connected together externally. Connect DGND to AGND at a single point in the system as close as possible to the MAX5952. supply also contains an undervoltage lockout (V DDUVLO ). The MAX5952 also features three other undervoltage and overvoltage interrupts: VEE undervoltage interrupt (V EEUV ), V DD undervoltage interrupt (VDDUV), and VDD overvoltage interrupt (VDDOV). A fault latches into the supply events register (Table 12), but the MAX5952 does not shut down the ports with VEEUV, VDDUV, or VDDOV. MAX5952 DC Disconnect Monitoring Setting R13h[DCD_EN_] bits high enable DC load monitoring during a normal powered state. If VRS (the voltage across RS) falls below the DC load disconnect threshold, VDCTH, for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port. AC Disconnect Monitoring The MAX5952 features AC load disconnect monitoring. Connect an external sine wave to OSC. The oscillator requirements are: 1) Frequency x VP-P = 200VP-P x Hz 15% 2) Positive peak voltage > +2V 3) Frequency > 60Hz A 100Hz 10%, 2VP-P 5%, with +1.2V offset (VPEAK = +2.2V typical) is recommended. The MAX5952 buffers and amplifies 3x the external oscillator signal and sends the signal to DET_, where the sine wave is AC-coupled to the output. The MAX5952 senses the presence of the load by monitoring the amplitude of the AC current returned to DET_ (see the Functional Diagram). Setting R13h[ACD_EN_] bits high enable AC load disconnect monitoring during a normal powered state. If the AC current peak at the DET_ input falls below IACTH for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port. IACTH is programmable using R23h[0-3]. An internal comparator checks for a proper amplitude of the oscillator input. If the positive peak of the input sinusoid falls below a safety value of 2V, OSC_FAIL sets and the port shuts down. Power cannot be applied to the ports when ACD_EN is set high and OSC_FAIL is set high. Leave OSC unconnected or connect it to DGND when not using AC-disconnect detection. Hardware Shutdown SHD_ shuts down the respective ports without using the serial interface. Hardware shutdown offers an emergency turn-off feature that allows a fast disconnect of the power supply from the port. Pull SHD_ low to remove power. SHD_ also resets the corresponding events and status register bits. Interrupt The MAX5952 contains an open-drain logic output (INT) that goes low when an interrupt condition exists. R00h and R01h (Tables 6 and 7) contain the definitions of the interrupt registers. The mask register R01h determines events that trigger an interrupt. As a response to an interrupt, the controller reads the status of the event register to determine the cause of the interrupt and takes subsequent actions. Each interrupt event register also contains a Clear on Read (CoR) register. Reading through the CoR register address clears the interrupt. INT remains low when reading the interrupt through the read-only addresses. For example, to clear a startup fault on the port 4 read address 09h (see Table 11). Use the global pushbutton bit in register 1Ah (bit 7, Table 23) to clear interrupts, or use a software or hardware reset. Undervoltage and Overvoltage Protection The MAX5952 contains several undervoltage and overvoltage protection features. Table 12 in the Register Map and Description section shows a detailed list of the undervoltage and overvoltage protection features. An internal VEE undervoltage lockout (VEEUVLO) circuit keeps the MOSFET off and the MAX5952 in reset until VAGND - VEE exceeds 29V for more than 3ms. An internal VEE overvoltage (VEE_OV) circuit shuts down the ports when (VAGND - VEE) exceeds 60V. The digital Thermal Shutdown If the MAX5952 die temperature reaches +150C, an overtemperature fault generates and the MAX5952 shuts down. The MOSFETs turn off. The die temperature of the MAX5952 must cool down below 130C to remove the overtemperature fault condition. After a thermal shutdown, the part is reset. 21 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Watchdog R1Dh, R1Eh, and R1F registers control the watchdog operation. The watchdog function, when enabled, allows the MAX5952 to gracefully take over control or securely shuts down the power to the ports in case of software/ firmware crashes. Contact the factory for more details. I2C-Compatible Serial Interface The MAX5952 operates as a slave that sends and receives data through an I 2C-compatible, 2-wire or 3-wire interface. The interface uses a serial-data input line (SDAIN), a serial-data output line (SDAOUT), and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX5952, and generates the SCL clock that synchronizes the data transfer. In most applications, connect the SDAIN and the SDAOUT lines together to form the serial-data line (SDA). Using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. The MAX5952 SDAIN line operates as an input. The MAX5952 SDAOUT operates as an open-drain output. A pullup resistor, typically 4.7k, is required on SDAOUT. The MAX5952 SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters, or if the master in a singlemaster system has an open-drain SCL output. Address Inputs A3, A2, A1, and A0 represent the four LSBs of the chip address. The complete chip address is 7 bits (see Table 4). Table 4. MAX5952 Address 0 1 0 A3 A2 A1 A0 R/W The four LSBs latch on the low-to-high transition of RESET or after a power-supply start (either on VDD or VEE). Address inputs default high through an internal 50k pullup resistor to VDD. The MAX5952 also responds to the call through a global address 30h (see the Global Addressing and Alert Response Protocol section). SDAIN tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 4. 2-Wire Serial Interface Timing Details SDAIN/SDA tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. 3-Wire Serial Interface Timing Details 22 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Serial Addressing Each transmission consists of a START condition (Figure 6) sent by a master, followed by the MAX5952 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition. START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master finishes communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The stop condition frees the bus for another transmission. Bit Transfer Each clock pulse transfers one data bit (Figure 7). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 8) that the recipient uses to handshake receipt of each byte of data. Thus each byte effectively transferred requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA (or the SDAOUT in the 3-wire interface) during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5952, the MAX5952 generates the acknowledge bit. When the MAX5952 transmits to the master, the master generates the acknowledge bit. MAX5952 SDA/ SDAIN SCL SDA SCL S START P STOP . DATA LINE STABLE; CHANGE OF DATA VALID DATA ALLOWED Figure 6. START and STOP Conditions Figure 7. Bit Transfer START CONDITION CLOCK PULSE FOR ACKNOWLEDGEMENT SCL 1 2 8 9 SDA BY TRANSMITTER S SDA BY RECEIVER Figure 8. Acknowledge ______________________________________________________________________________________ 23 High-Power, Quad, PSE Controller for Power-Over-Ethernet Slave Address The MAX5952 has a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for a read command. 010 always represents the first three bits (MSBs) of the MAX5952 slave address. Slave address bits A3, A2, A1, and A0 represent the states of the MAX5952's A3, A2, A1, and A0 inputs, allowing up to sixteen MAX5952 devices to share the bus. The states of the A3, A2, A1 and A0 latch in upon the reset of the MAX5952 into register R11h. The MAX5952 monitors the bus continuously, waiting for a START condition followed by the MAX5952's slave address. When a MAX5952 recognizes its slave address, the MAX5952 acknowledges and is then ready for continued communication. Global Addressing and Alert Response Protocol The global address call is used in writing mode to write the same register to multiple devices (address 0x60). In read mode (address 0x61), the global address call is used as the alert response address. When responding to a global call, the MAX5952 puts out on the data line its own address whenever its interrupt is active. So does every other device connected to the SDAOUT line that has an active interrupt. After every bit transmitted, the MAX5952 checks that the data line effectively corresponds to the data it is delivering. If it is not, it then backs off and frees the data line. This litigation protocol always allows the part with the lowest address to complete the transmission. The microcontroller can then MAX5952 respond to the interrupt and take proper actions. The MAX5952 does not reset its own interrupt at the end of the alert response protocol. The microcontroller has to do it by clearing the event register through their CoR adresses or activating the CLR_INT pushbutton. Message Format for Writing to the MAX5952 A write to the MAX5952 comprises of the MAX5952's slave address transmission with the R/W bit set to 0, followed by at least one byte of information. The first byte of information is the command byte (Figure 10). The command byte determines which register of the MAX5952 is written to by the next byte, if received. If the MAX5952 detects a STOP condition after receiving the command byte, the MAX5952 takes no further action beyond storing the command byte. Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX5952 selected by the command byte. If the MAX5952 transmits multiple data bytes before the MAX5952 detects a STOP condition, these bytes store in subsequent MAX5952 internal registers because the control byte address auto-increments. Any bytes received after the control byte are data bytes. The first data byte goes into the internal register of the MAX5952 selected by the control byte (Figure 7). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are stored in subsequent MAX5952 internal registers because the control byte address auto-increments. MSB SDA 0 1 0 A3 A2 A1 LSB A0 R/W ACK SCL Figure 9. Slave Address CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX5952 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 CONTROL BYTE ACKNOWLEDGE FROM MAX5952 A P Figure 10. Control Byte Received 24 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Message Format for Reading The MAX5952 reads using the MAX5952's internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. The pointer auto-increments after reading each data byte using the same rules as for a write. Thus, a read is initiated by first configuring the MAX5952's command byte by performing a write (Figure 11). The master now reads `n' consecutive bytes from the MAX5952, with the first data byte read from the register addressed by the initialized command byte (Figure 12). When performing read-after-write verification, remember to reset the command byte's address because the stored control byte address auto-increments after the write. Operation with Multiple Masters When the MAX5952 operates on a 2-wire interface with multiple masters, a master reading the MAX5952 should use repeated starts between the write which sets the MAX5952's address pointer, and the read(s) that take the data from the location(s). It is possible for master 2 to take over the bus after master 1 has set up the MAX5952's address pointer but before master 1 has read the data. If master 2 subsequently resets the MAX5952's address pointer then master 1's read may be from an unexpected location. Command Address Auto-Incrementing Address auto-incrementing allows the MAX5952 to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX5952 generally increments after each data byte is written or read (Table 4). The MAX5952 is designed to prevent overwrites on unavailable register addresses and unintentional wrap-around of addresses. MAX5952 Table 5. Auto-Increment Rules COMMAND BYTE ADDRESS RANGE 0x00 to 0x26 0x26 AUTO-INCREMENT BEHAVIOR Command address auto-increments after byte read or written Command address remains at 0x26 after byte written or read ACKNOWLEDGE FROM MAX5952 HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM MAX5952 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 ACKNOWLEDGE FROM MAX5952 D5 D4 D3 D2 D1 D0 CONTROL BYTE A DATA BYTE 1 BYTE A P AUTO-INCREMENT MEMORY WORD ADDRESS Figure 11. Control and Single Data Byte Received ACKNOWLEDGE FROM MAX5952 HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM MAX5952 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 ACKNOWLEDGE FROM MAX5952 D5 D4 D3 D2 D1 D0 CONTROL BYTE A DATA BYTE n BYTES A P AUTO-INCREMENT MEMORY WORD ADDRESS Figure 12. `n' Data Bytes Received ______________________________________________________________________________________ 25 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Register Map and Description The interrupt register (Table 6) summarizes the event register status and is used to send an interrupt signal (INT goes low) to the controller. Writing a 1 to R1Ah[7] clears all interrupt and events registers. A reset sets R00h to 00h. INT_EN (R17h[7]) is a global interrupt mask (Table 7). The MASK_ bits activate the corresponding interrupt bits in register R00h. Writing a 0 to INT_EN (R17h[7]) disables the INT output. A reset sets R01h to AAA00A00b where A is the state of the AUTO input prior to the reset. Table 6. Interrupt Register ADDRESS = 00h SYMBOL SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R DESCRIPTION Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh (Table 12). Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h (Table 11). Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register R06h/R07h (Table 10). Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register R04h/R05h (Table 9). Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register R04h/R05h (Table 9). Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h (Table 10). Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h (Table 8). Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register R02h/R03h (Table 8). Table 7. Interrupt Mask Register ADDRESS = 01h SYMBOL MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Interrupt mask bit 7. A logic-high enables the SUP_FLT interrupts. A logic-low disables the SUP_FLT interrupts. Interrupt mask bit 6. A logic-high enables the TSTR_FLT interrupts. A logic-low disables the TSTR_FLT interrupts. Interrupt mask bit 5. A logic-high enables the IMAX_FLT interrupts. A logic-low disables the IMAX_FLT interrupts. Interrupt mask bit 4. A logic-high enables the CL_END interrupts. A logic-low disables the CL_END interrupts. Interrupt mask bit 3. A logic-high enables the DET_END interrupts. A logic-low disables the DET_END interrupts. Interrupt mask bit 2. A logic-high enables the LD_DISC interrupts. A logic-low disables the LD_DISC interrupts. Interrupt mask bit 1. A logic-high enables the PG_INT interrupts. A logic-low disables the PG_INT interrupts. Interrupt mask bit 0. A logic-high enables the PEN_INT interrupts. A logic-low disables the PEN_INT interrupts. 26 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet The power event register (Table 8) records changes in the power status of the four ports. Any change in PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1. PG_CHG_ and PWEN_CHG_ trigger on the edges of PGOOD_ and PWR_EN_ and do not depend on the actual level of the bits. The power event register has two addresses. When read through the R02h address, the content of the register is left unchanged. When read through the CoR R03h address, the register content is cleared. A reset sets R02h/R03h = 00h. MAX5952 Table 8. Power Event Register ADDRESS = SYMBOL PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1 PWEN_CHG4 PWEN_CHG3 PWEN_CHG2 PWEN_CHG1 BIT 7 6 5 4 3 2 1 0 02h R/W R R R R R R R R 03h R/W CoR CoR CoR CoR CoR CoR CoR CoR DESCRIPTION PGOOD change event for port 4 PGOOD change event for port 3 PGOOD change event for port 2 PGOOD change event for port 1 Power enable change event for port 4 Power enable change event for port 3 Power enable change event for port 2 Power enable change event for port 1 DET_END_/CL_END_ is set high whenever detection/ classification is completed on the corresponding port. A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1 in any of the DET_END_ bits forces R00h[3] to 1. As with any of the other events register, the detect event regis- ter has two addresses. When read through the R04h address, the content of the register is left unchanged. When read through the CoR R05h address, the register content is cleared. A reset sets R04h/R05h = 00h. Table 9. Detect Event Register ADDRESS = SYMBOL CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1 BIT 7 6 5 4 3 2 1 0 04h R/W R R R R R R R R 05h R/W CoR CoR CoR CoR CoR CoR CoR CoR DESCRIPTION Classification completed on port 4 Classification completed on port 3 Classification completed on port 2 Classification completed on port 1 Detection completed on port 4 Detection completed on port 3 Detection completed on port 2 Detection completed on port 1 ______________________________________________________________________________________ 27 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 LD_DISC_ is set high whenever the corresponding port shuts down due to detection of load removal. IMAX_FLT_ is set high when the port shuts down due to an extended overcurrent event after a successful startup. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1. A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1. As with any of the other events register, the fault event register has two addresses. When read through the R06h address, the content of the register is left unchanged. When read through the CoR R07h address, the register content is cleared. A reset sets R06h/R07h = 00h. Table 10. Fault Event Register ADDRESS = SYMBOL LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1 BIT 7 6 5 4 3 2 1 0 06h R/W R R R R R R R R 07h R/W CoR CoR CoR CoR CoR CoR CoR CoR Disconnect on port 4 Disconnect on port 3 Disconnect on port 2 Disconnect on port 1 Overcurrent on port 4 Overcurrent on port 3 Overcurrent on port 2 Overcurrent on port 1 DESCRIPTION If the port remains in current limit or the PGOOD condition is not met at the end of the startup period, the port shuts down and the corresponding STRT_FLT_ is set to 1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1. IVC_ is set to 1 whenever the port current exceeds the maximum allowed limit for the class (determined during the classification process). A 1 in any of IVC_ forces R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1, the port also limits the load current according to its class as specified in the Electrical Characteristics table. As with any of the other events register, the startup event register has two addresses. When read through the R08h address, the content of the register is left unchanged. When read through the CoR R09h address, the register content is cleared. A reset sets R08h/R09h = 00h. Table 11. Startup Event Register ADDRESS = SYMBOL IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1 BIT 7 6 5 4 3 2 1 0 08h R/W R R R R R R R R 09h R/W CoR CoR CoR CoR CoR CoR CoR CoR DESCRIPTION Class overcurrent flag for port 4 Class overcurrent flag for port 3 Class overcurrent flag for port 2 Class overcurrent flag for port 1 Startup failed on port 4 Startup failed on port 3 Startup failed on port 2 Startup failed on port 1 28 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet The MAX5952 continuously monitors the power supplies and sets the appropriate bits in the supply event register (Table 12). VDD_OV/VEE_OV is set to 1 whenever V DD /V EE exceeds its overvoltage threshold. V DD_UV /V EE_UV is set to 1 whenever V DD /V EE falls below its undervoltage threshold. OSC_FAIL is set to 1 whenever the amplitude of the oscillator signal at the OSC_ input falls below a level that might compromise the AC disconnect detection function. OSC_FAIL generates an interrupt only if at least one of the ACD_EN (R13h[7:4]) bits is set high. A thermal shutdown circuit monitors the temperature of the die and resets the MAX5952 if the temperature exceeds +150C. TSD is set to 1 after the MAX5952 returns to normal operation. TSD is also set to 1 after every UVLO reset. When VDD and/or |VEE| is below its UVLO threshold, the MAX5952 is in reset mode and securely holds all ports off. When VDD and |VEE| rise to above their respective UVLO thresholds, the device comes out of reset as soon as the last supply crosses the UVLO threshold. The last supply corresponding UV and UVLO bits in the supply event register is set to 1. A 1 in any supply event register's bits forces R00h[7] to 1. As with any of the other events register, the supply event register has two addresses. When read through the R0Ah address, the content of the register is left unchanged. When read through the CoR R0Bh address, the register content is cleared. A reset sets R0Ah/R0Bh to 10100001b if VDD comes up after VEE or to 10010100b if VEE comes up after VDD. MAX5952 Table 12. Supply Event Register ADDRESS = SYMBOL TSD VDD_OV VDD_UV VEE_UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO BIT 7 6 5 4 3 2 1 0 0Ah R/W R R R R R R R R 0Bh R/W CoR CoR CoR CoR CoR CoR CoR CoR Overtemperature shutdown VDD overvoltage condition VDD undervoltage condition VEE undervoltage lockout condition VEE overvoltage condition VEE undervoltage condition Oscillator amplitude is below limit VDD undervoltage lockout condition DESCRIPTION ______________________________________________________________________________________ 29 High-Power, Quad, PSE Controller for Power-Over-Ethernet The port status register (Table 13a) records the results of the detection and classification at the end of each phase in three encoding bits each. R0Ch contains the detection and classification status of port 1. R0Dh corresponds to port 2, R0Eh corresponds to port 3, and R0Fh corresponds to port 4. Tables 13b and 13c show the detection/classification result decoding charts, respectively. For CLC_EN = 0, the detection result is shown in Table 13b. When CLC_EN is set high, the MAX5952 allows valid detection of high capacitive load of up to 100F. MAX5952 When ping-pong classification is not enabled (ENx_CL6 = 0), the classification status is reported in Table 13c. When ping-pong classification is enabled (ENx_CL6 = 1), the CLASS_[2:0] bits are set to 000 and the classification result is reported in locations R2Ch-R2Fh. As a protection, when POFF_CL (R17h[3], Table 18) is set to 1, the MAX5952 prohibits turning on power to the port that returns a status 111 after classification. A reset sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h. Table 13a. Port Status Registers ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh SYMBOL Reserved CLASS_ Reserved DET_ST_ BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Reserved CLASS_[2] CLASS_[1] CLASS_[0] Reserved DET_[2] DET_[1] DET_[0] DESCRIPTION Table 13b. Detection Result Decoding Chart DET_ST_[2:0] (ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh) 000 001 010 011 100 101 110 111 DETECTED None DCP HIGH CAP RLOW DET_OK RHIGH OPEN0 DCN Detection status unknown Positive DC supply connected at the port (AGND - VOUT_ < 1V) High capacitance at the port (> 8.5F) Low resistance at the port, RPD < 15k Detection pass, 15k > RPD > 33k High resistance at the port, RPD > 33k Open port (I < 10A) Negative DC supply connected to the port (VOUT - VEE < 2V) DESCRIPTION Table 13c. Classification Result Decoding Chart CLASS_[2:0] (ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh) 000 001 010 011 100 101 110 111 CLASS RESULT Unknown 1 2 3 4 5 0 Current limit (> ICILIM) 30 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet PGOOD_ is set to 1 (Table 14) at the end of the powerup startup period if the power-good condition is met (0 < (VOUT - VEE) < PGTH). The power-good condition must remain valid for more than t PGOOD to assert PGOOD_. PGOOD_ is reset to 0 whenever the output falls out of the power-good condition. A fault condition immediately forces PGOOD_ low. PWR_EN_ is set to 1 when the port power is turned on. PWR_EN resets to 0 as soon as the port turns off. Any transition of PGOOD_ and PWR_EN_ bits set the corresponding bit in the power event registers R02h/R03h (Table 8). A reset sets R10h = 00h. MAX5952 Table 14. Power Status Register ADDRESS = 10h SYMBOL PGOOD4 PGOOD3 PGOOD2 PGOOD1 PWR_EN4 PWR_EN3 PWR_EN2 PWR_EN1 BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Power-good condition on port 4 Power-good condition on port 3 Power-good condition on port 2 Power-good condition on port 1 Power is enabled on port 4 Power is enabled on port 3 Power is enabled on port 2 Power is enabled on port 1 DESCRIPTION A3, A2, A1, A0 (Table 15) represent the four LSBs of the MAX5952 address (Table 4). During a reset, the device latches into R11h. These four bits address from the corresponding inputs as well as the state of the MIDSPAN and AUTO inputs. Changes to those inputs during normal operation are ignored. Table 15. Address Input Status Register ADDRESS = 11h SYMBOL Reserved Reserved A3 A2 A1 A0 MIDSPAN AUTO BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Reserved Reserved Device address, A3 pin latched-in status Device address, A2 pin latched-in status Device address, A1 pin latched-in status Device address, A0 pin latched-in status MIDSPAN input's latched-in status AUTO input's latched-in status DESCRIPTION ______________________________________________________________________________________ 31 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 The MAX5952 uses two bits for each port to set the mode of operation. Set the modes according to Table 16. A reset sets R12h = AAAAAAAA where A represents the latched-in state of the AUTO input prior to the reset. Use software to change the mode of operation. Software resets of ports (RESET_P_ bit, Table 23) do not affect the mode register. Table 16. Mode Register ADDRESS = 12h SYMBOL P4_M1 P4_M0 P3_M1 P3_M0 P2_M1 P2_M0 P1_M1 P1_M0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W MODE[1] for port 4 MODE[0] for port 4 MODE[1] for port 3 MODE[0] for port 3 MODE[1] for port 2 MODE[0] for port 2 MODE[1] for port 1 MODE[0] for port 1 DESCRIPTION Table 16a. Mode Status MODE 00 01 10 11 Shutdown Manual Semi-auto Auto DESCRIPTION Setting DCD_EN_ to 1 enables the DC load disconnect detection feature (Table 17). Setting ACD_EN_ to 1 enables the AC load disconnect feature. If enabled, the load disconnect detection starts during power mode and after startup when the corresponding PGOOD_ bit in register R10h (Table 14) goes high. A reset sets R13h = 0000AAAA where A represents the latched-in state of the AUTO input prior to the reset. Table 17. Load Disconnect Detection Enable Register ADDRESS = 13h SYMBOL ACD_EN4 ACD_EN3 ACD_EN2 ACD_EN1 DCD_EN4 DCD_EN3 DCD_EN2 DCD_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Enable AC disconnect detection on port 4 Enable AC disconnect detection on port 3 Enable AC disconnect detection on port 2 Enable AC disconnect detection on port 1 Enable DC disconnect detection on port 4 Enable DC disconnect detection on port 3 Enable DC disconnect detection on port 2 Enable DC disconnect detection on port 1 32 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Setting DET_EN_/CLASS_EN_ to 1 (Table 18) enables load detection/classification, respectively. Detection always has priority over classification. To perform classification without detection, set the DET_EN_ bit low and CLASS_EN_ bit high. In manual mode, R14h works like a pushbutton. Set the bits high to begin the corresponding routine. The bit clears after the routine finishes. When entering auto mode, R14h defaults to FFh. When entering semi or manual modes, R14h defaults to 00h. A reset or power-up sets R14h = AAAAAAAAb where A represents the latched-in state of the AUTO input prior to the reset. MAX5952 Table 18. Detection and Classification Enable Register ADDRESS = 14h SYMBOL CLASS_EN4 CLASS_EN3 CLASS_EN4 CLASS_EN3 DET_EN4 DET_EN3 DET_EN2 DET_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable classification on port 4 Enable classification on port 3 Enable classification on port 2 Enable classification on port 1 Enable detection on port 4 Enable detection on port 3 Enable detection on port 2 Enable detection on port 1 DESCRIPTION EN_HP_CL_, EN_HP_ALL together with CL_DISC (R17h[2]) and ENx_CL6 (R1Ch[7:4]) are used to program the high-power mode. See Table 3 for details. Setting BCKOFF_ to 1 (Table 19) enables cadence timing on each port where the port backs off and waits 2.2s after each failed load discovery detection. The IEEE 802.3af standard requires a PSE that delivers power through the spare pairs (midspan PSE) to have cadence timing. A reset or power-up sets R15h = 0000XXXXb where `X' is the logic AND of the MIDSPAN and AUTO inputs. Table 19. Backoff and High-Power Enable Register ADDRESS = 15h SYMBOL BCKOFF4 BCKOFF3 BCKOFF2 BCKOFF1 BIT 3 2 1 0 R/W R/W R/W R/W R/W DESCRIPTION Enable cadence timing on port 4 Enable cadence timing on port 3 Enable cadence timing on port 2 Enable cadence timing on port 1 ______________________________________________________________________________________ 33 High-Power, Quad, PSE Controller for Power-Over-Ethernet TSTART[1,0] (Table 20a) programs the startup timers. Startup time is the time the port is allowed to be in current limit during startup. TFAULT_[1,0] programs the fault time. Fault time is the time allowed for the port to be in current limit during normal operation. RSTR[1,0] programs the discharge rate of the TFAULT_ counter and effectively sets the time the port remains off after an overcurrent fault. TDISC[1,0] programs the load disconnect detection time. The device turns off power to the port if it fails to provide a minimum power maintenance signal for longer than the load disconnect detection time (TDISC). Set the bits in R16h to scale the TSTART, TFAULT, and TDISC to a multiple of their nominal value specified in the Electrical Characteristics table. When the MAX5952 shuts down a port due to an extended overcurrent condition (either during startup or normal operation), if RSRT_EN is set high, the part does not allow the port to power back on before the restart timer (Table 20b) returns to zero. This effectively sets a minimum duty cycle that protects the external MOSFET from overheating during a prolonged output overcurrent conditions. A reset sets R16h = 00h. MAX5952 Table 20a. Timing Register ADDRESS = 16h SYMBOL RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0] BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Restart timer programming bit 1 Restart timer programming bit 0 Startup timer programming bit 1 Startup timer programming bit 0 Overcurrent timer programming bit 1 Overcurrent timer programming bit 0 Load disconnect timer programming bit 1 Load disconnect timer programming bit 0 DESCRIPTION Table 20b. Startup, Fault, and Load Disconnect Timer Values for Timing Register BIT [1:0] (ADDRESS = 16h) 00 01 10 11 RSTR 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 x tFAULT tDISC tDISC nominal (350ms, typ) 1/4 x tDISC nominal 1/2 x tDISC nominal 2 x tDISC nominal tSTART tSTART nominal (60ms, typ) 1/2 x tSTART nominal 2 x tSTART nominal 4 x tSTART nominal tFAULT tFault nominal (60ms, typ) 1/2 x tFAULT nominal 2 x tFAULT nominal 4 x tFAULT nominal 34 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Setting CL_DISC to 1 (Table 21) enables port over class current protection, where MAX5952 scales down the overcurrent limit (VFLT_LIM) according to the port classification status. This feature provides protection to the system against PDs that violate their maximum class current allowance. The higher current setting is enabled only after a successful startup so that the PD powers up as a normal 15W device. CL_DISC, together with EN_HP_CL_ (R15h [6:4]), EN_HP_ALL (R15h [7]), and ENx_CL6 (R1Ch [7:4]) are used to program the high-power mode. See Table 3 for details. Setting OUT_ISO high (Table 21), forces DET_ to a high-impedance state. A reset sets R17h = 0xC0. MAX5952 Table 21. Miscellaneous Configurations 1 ADDRESS = 17h SYMBOL INT_EN RSTR_EN Reserved Reserved POFF_CL CL_DISC OUT_ISO BIT 7 6 5 4 3 2 1 R/W R/W R R R R R/W R/W A logic-high enables INT functionality A logic-high enables the autorestart protection time off (as set by the RSRT[1:0] bits) Reserved Reserved A logic-high prevents power-up after a classification failure (I > 50mA, valid only in AUTO mode) A logic-high enables reduced current-limit voltage threshold (VFLT_LIM) according to port Forces DET_ to high impedance. Does not interfere with other circuit operation. DESCRIPTION Power-enable pushbutton for semi and manual modes is found in Table 22. Setting PWR_ON_ to 1 turns on power to the corresponding port. Setting PWR_OFF_ to 1 turns off power to the port. PWR_ON is ignored when the port is already powered and during shutdown. PWR_OFF is ignored when the port is already off and during shutdown. After execution, the bits reset to 0. During detection or classification, if PWR_ON_ goes high, the MAX5952 gracefully terminates the current operation and turns on power to the port. The MAX5952 ignores the PWR_ON_ in auto mode. A reset sets R19h = 00h. Table 22. Power-Enable Pushbuttons ADDRESS = 19h SYMBOL PWR_OFF4 PWR_OFF3 PWR_OFF2 PWR_OFF1 PWR_ON4 PWR_ON3 PWR_ON2 PWR_ON1 BIT 7 6 5 4 3 2 1 0 R/W W W W W W W W W A logic-high powers off port 4 A logic-high powers off port 3 A logic-high powers off port 2 A logic-high powers off port 1 A logic-high powers on port 4 A logic-high powers on port 3 A logic-high powers on port 2 A logic-high powers on port 1 DESCRIPTION ______________________________________________________________________________________ 35 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Writing a 1 to CLR_INT (Table 23) clears all the event registers and the corresponding interrupt bits in register R00h. Writing a 1 to RESET_P_ turns off power to the corresponding port and resets only the status and event registers of that port. After execution, the bits reset to 0. Writing a 1 to RESET_IC causes a global software reset, after which the register map is set back to its reset state. A reset sets R1Ah = 00h. Table 23. Global Pushbuttons ADDRESS = 1Ah SYMBOL CLR_INT Reserved Reserved RESET_IC RESET_P4 RESET_P3 RESET_P2 RESET_P1 BIT 7 6 5 4 3 2 1 0 W W W W W R/W W A logic-high clears all interrupts Reserved Reserved A logic-high resets the MAX5952 A logic-high softly resets port 4 A logic-high softly resets port 3 A logic-high softly resets port 2 A logic-high softly resets port 1 DESCRIPTION The ID register (Table 24) keeps track of the device ID number and revision. The MAX5952's ID_CODE[4:0] = 11000b. Contact the factory for REV[2:0] value. Table 24. ID Register ADDRESS = 1Bh SYMBOL BIT 7 6 ID_CODE 5 4 3 2 REV 1 0 R/W R R R R R R R R ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV [2] REV [1] REV [0] DESCRIPTION 36 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Enable the SMODE function (Table 25) by setting EN_WHDOG (R1Fh[7]) to 1. SMODE_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. SMODE_ also goes high each and every time the software tries to power on a port, but is denied since the port is in hardware mode. A reset sets R1Ch = 00h. MAX5952 Table 25. SMODE Enable Register ADDRESS = 1Ch SYMBOL SMODE4 SMODE3 SMODE2 SMODE1 BIT 3 2 1 0 CoR CoR CoR CoR CoR Port 4 hardware control flag Port 3 hardware control flag Port 2 hardware control flag Port 1 hardware control flag DESCRIPTION Set EN_WHDOG (R1Fh[7]) to 1 to enable the watchdog function. When activated, the watchdog timer counter, WDTIME[7:0], continuously decrements toward zero once every 164ms. Once the counter reaches zero (also called watchdog expiry), the MAX5952 enters hardware-controlled mode and each port shifts to a mode set by the HWMODE_ bit in register R1Fh (Table 27). Use software to set WDTIME (Table 26) and continuously set this register to some nonzero value before the register reaches zero to prevent a watchdog expiry. In this way, the software gracefully manages the power to ports upon a system crash or switchover. While in hardware-controlled mode, the MAX5952 ignores all requests to turn the power on and the flag SMODE_ indicates that the hardware has taken control of the MAX5952 operation. In addition, the software is not allowed to change the mode of operation in hardware-controlled mode. A reset sets R1Eh = 00h. Table 26. Watchdog Register ADDRESS = 1Eh SYMBOL BIT 7 6 5 WDTIME 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] DESCRIPTION ______________________________________________________________________________________ 37 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Setting EN_WHDOG (Table 27) high activates the watchdog counter. When the counter reaches zero, the port switches to the hardware-controlled mode determined by the corresponding HWMODE_ bit. A low in HWMODE_ switches the port into shutdown by setting the bits in register R12h to 00. A high in HWMODE_ switches the port into auto mode by setting the bits in register R12h to 11. If WD_INT_EN is set, an interrupt is sent if any of the SMODE bits are set. A reset sets R1Fh = 00h. Table 27. Switch Mode Register ADDRESS = 1Fh SYMBOL EN_WHDOG WD_INT_EN Reserved Reserved HWMODE4 HWMODE3 HWMODE2 HWMODE1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W -- R/W R/W R/W R/W R/W Enables interrupt on SMODE_ bits Reserved Reserved Port 4 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 3 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 2 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 1 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires DESCRIPTION A logic-high enables the watchdog function The CLC_EN enables the large capacitor detection feature. When CLC_EN is set the device can recognize a capacitor load up to 100F. If the CLC_EN is reset, the MAX5952 performs normal detection. AC_TH allows programming of the threshold of the AC disconnect comparator. The threshold is defined as a current since the comparators verify that the peak of the current pulses sensed at the DET_ input exceed a preset threshold. The current threshold is defined as follows: IAC_TH = 226.68A + 28.33 x NAC_TH where NAC_TH is the decimal value of AC_TH. When set low, DET_BY inhibits port power-on if the discovery detection was bypassed in auto mode. When set high, DET_BY allows the device to turn on power to a non-IEEE 802.3af load without doing detection. If OSCF_RS is set high, the OSC_FAIL bit is ignored. A reset or power-up sets R23h = 04h. Default IAC_TH is 340A. Table 28. Program Register ADDRESS = 23h SYMBOL Reserved Reserved CLC_EN DET_BY OSCF_RS AC_TH BIT 7 6 5 4 3 2 1 0 R/W -- -- R/W R/W R/W R/W R/W R/W Reserved Reserved Large capacitor detection enable Enables skipping detection in AUTO mode OSC_FAIL reset bit AC_TH[2] AC_TH[1] AC_TH[0] DESCRIPTION 38 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Table 29. High-Power Mode Register ADDRESS = 24h SYMBOL BIT 7 3 Reserved 2 1 0 R/W -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved DESCRIPTION Table 30. Reserved ADDRESS = 25h SYMBOL BIT 7 6 5 Reserved 4 3 2 1 0 R/W -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION Table 31. Reserved ADDRESS = 26h SYMBOL BIT 7 6 5 Reserved 4 3 2 1 0 R/W -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION ______________________________________________________________________________________ 39 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 The IVEE bits enable the current-limit scaling (Table 32). This feature is used to reduce the current limit for systems running at higher voltage to maintain the desired output power. Table 33 sets the current-limit scaling register. A reset or power-up sets R29h = 00h. Table 32. Miscellaneous Configurations 2 ADDRESS = 29h SYMBOL BIT 7 6 Reserved 5 4 3 2 IVEE 1 0 R/W -- -- -- -- -- -- R/W R/W DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved IVEE[1] IVEE[0] Table 33. Current-Limit Scaling Register IVEE[1:0] (ADDRESS = 29h) 00 01 10 11 CURRENT LIMIT (%) Default -5 -10 -15 The three ICUT_ bits (Tables 34a and 34b) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE 802.3af standard limit. The MAX5952 can automatically set the ICUT register or can be manually written to by the software (see Table 3). Class 1 and 2 limits can also be programmed by software independently from the classification status. See Table 3. A reset or power-up sets R2Ah = R2Bh = 00h. Table 34a. ICUT Registers 1 and 2 ADDRESS = 2Ah SYMBOL Reserved ICUT2 Reserved ICUT1 BIT 7 6 5 4 3 2 1 0 R/W -- R/W R/W R/W -- R/W R/W R/W Reserved ICUT2[2] ICUT2[1] ICUT2[0] Reserved ICUT1[2] ICUT1[1] ICUT1[0] DESCRIPTION Table 34b. ICUT Registers 3 and 4 ADDRESS = 2Bh SYMBOL Reserved ICUT4 Reserved ICUT3 BIT 7 6 5 4 3 2 1 0 R/W -- R/W R/W R/W -- R/W R/W R/W Reserved ICUT4[2] ICUT4[1] ICUT4[0] Reserved ICUT3[2] ICUT3[1] ICUT3[0] DESCRIPTION 40 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Table 34c. ICUT Register Bit Values for Current-Limit Threshold ICUT_[2:0] (ADDRESS = 2Ah, 2Bh) 000 001 010 011 100 101 110 111 SCALE FACTOR 1x 1.5x 1.75x 2x 2.25x 2.5x 0.3x 0.53x TYPICAL CURRENT-LIMIT THRESHOLD (mA) 375 563 656 750 844 938 Class 1 Class 2 Table 35. Classification Status Registers ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh SYMBOL Reserved BIT 7 6 R/W -- -- Reserved Reserved DESCRIPTION The MAX5952 provides current readout for each port during classification and normal power mode. The current per port information is separated into 9 bits. They are organized into 2 consecutive registers for each one of the ports. The information can be quickly retrieved using the auto-increment option of the address pointer. To avoid the LSB register changing while reading the MSB, the information is frozen once the addressing byte points to any of the current readout registers. During power mode, the current value can be calculated as IPORT = NIPD_ x 1.953125mA During classification, the current is ICLASS = NIPD_ x 0.0975mA where NIPD is the decimal value of the 9-bit word. The ADC saturates both at full scale and at zero. A reset sets R30h-R37h = 00h. Table 36. Current Registers ADDRESS = 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h SYMBOL BIT 7 6 5 IPD_ 4 3 2 1 0 R/W W W W W W W W W IPD_[8] IPD_[7] IPD_[6] IPD_[5] IPD_[4] IPD_[3] IPD_[2] IPD_[1]/IPD_[0] DESCRIPTION ______________________________________________________________________________________ 41 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Table 37. Register Summary ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE INTERRUPTS 00h 01h EVENTS 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh STATUS 0Ch 0Dh 0Eh 0Fh 10h 11h Port 1 Status Port 2 Status Port 3 Status Port 4 Status Power Status Pin Status RO RO RO RO RO RO 1 2 3 4 4321 G Reserved Reserved Reserved Reserved PGOOD4 Reserved CLASS1[2] CLASS2[2] CLASS3[2] CLASS4[2] PGOOD3 Reserved CLASS1[1 CLASS2[1 CLASS3[1 CLASS4[1 PGOOD2 A3 CLASS1[0] CLASS2[0] CLASS3[0] CLASS4[0] PGOOD1 A2 Reserved Reserved Reserved Reserved PWR_EN4 A1 DET_ST1[2] DET_ST2[2] DET_ST3[2] DET_ST4[2] PWR_EN3 A0 DET_ST1[1] DET_ST2[1] DET_ST3[1] DET_ST4[1] PWR_EN2 MIDSPAN DET_ST1[0] DET_ST2[0] DET_ST3[0] DET_ST4[0] PWR_EN1 AUTO 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2, A1A0MA Power Event Power Event CoR Detect Event Detect Event CoR Fault Event Fault Event CoR Tstart Event Tstart Event CoR Supply Event Supply Event CoR RO CoR RO CoR RO CoR RO CoR RO CoR 4321 4321 4321 4321 4321 PG_CHG4 CL_END4 PG_CHG3 CL_END3 PG_CHG2 CL_END2 PG_CHG1 CL_END1 PWEN_ CHG4 DET_END4 PWEN_ CHG3 DET_END3 PWEN_ CHG2 DET_END2 PWEN_ CHG1 DET_END1 0000,0000 0000,0000 Interrupt Int Mask RO R/W G G SUP_FLT MASK7 TSTR_FLT MASK6 IMAX_FLT MASK5 CL_END MASK4 DET_END MASK3 LD_DISC MASK2 PG_INT MASK1 PE_INT MASK0 0000,0000 AAA0,0A00 LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1 0000,0000 IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1 0000,0000 TSD VDD_OV VDD_UV VEE_UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO 0001,0000* CONFIGURATION 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1EH 1FH Operating Mode Disconnect Enable Det/Class Enable Backoff Enable Timing Config Misc Config 1 Reserved Power Enable Global ID SMODE Register Reserved Watchdog Register Switch Mode Register R/W R/W R/W R/W R/W R/W R/W R/W R/W WO WO RO CoR 4321 4321 4321 4321 G G G 4321 G G 4321 G G 4321 P4_M1 ACD_EN4 CLASS_EN4 -- RSRT[1] INT_EN Reserved PWR_OFF4 CLR_INT ID_CODE[4] -- Reserved WDTIME[7] EN_WHDOG P4_M0 ACD_EN3 CLASS_EN3 -- RSRT[0] RSRT_EN Reserved PWR_OFF3 Reserved ID_CODE[3] -- Reserved WDTIME[6] WD_INT_EN P3_M1 ACD_EN2 CLASS_E -- TSTART[1] Reserved Reserved PWR_OFF Reserved ID_CODE[ -- Reserved P3_M0 ACD_EN1 CLASS_EN -- TSTART[0] Reserved Reserved PWR_OFF RESET_IC ID_CODE[ -- Reserved P2_M1 DCD_EN4 DET_EN4 BCKOFF4 TFAULT[1] POFF_CL Reserved PWR_ON4 RESET_P4 ID_CODE[0 SMODE4 Reserved WDTIME[3] HWMODE4 P2_M0 DCD_EN3 DET_EN3 BCKOFF3 TFAULT[0] CL_DISC Reserved PWR_ON3 RESET_P3 REV [2] SMODE3 Reserved WDTIME[2] HWMODE3 P1_M1 DCD_EN2 DET_EN2 BCKOFF2 TDISC[1] OUT_ISO Reserved PWR_ON2 RESET_P2 REV [1] SMODE2 Reserved WDTIME[1] HWMODE2 P1_M0 DCD_EN1 DET_EN1 BCKOFF1 TDISC[0] HP_TIME Reserved PWR_ON1 RESET_P1 REV [0] SMODE1 Reserved WDTIME[0] HWMODE1 0000,0000 0000,0000 0000,0000 0000,0000 1100,0000 0000,0000 AAAA,AAAA 0000,AAAA AAAA,AAAA 0000,XXXX 0000,0000 1100,0000 PUSHBUTTONS GENERAL WDTIME[5 WDTIME[4 reserved CSCM 42 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Table 37. Register Summary (continued) ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE MAXIM RESERVED 20H 21H 22H 23H 24h 25h 26h 27H 28H 29H 2AH 2BH Reserved Reserved Reserved Program 1 High Power Mode Reserved Reserved Reserved Reserved Misc Config 2 ICUT Register 1 ICUT Register 2 R/W R/W R/W R/W R/W -- -- G G G 4321 G G G G G 1234 21 43 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved -- Reserved Reserved Reserved Reserved Reserved ICUT2[2] ICUT4[2] Reserved Reserved Reserved CLC_EN -- Reserved Reserved Reserved Reserved Reserved ICUT2[1] ICUT4[1] Reserved Reserved Reserved DET_BY -- Reserved Reserved Reserved Reserved Reserved ICUT2[0] ICUT4[0] Reserved Reserved Reserved OSCF_RS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC_TH[2] Reserved Reserved Reserved Reserved Reserved Reserved ICUT1[2] ICUT3[2] Reserved Reserved Reserved AC_TH[1] Reserved Reserved Reserved Reserved Reserved IVEE[1] ICUT1[1] ICUT3[1] Reserved Reserved Reserved AC_TH[0] Reserved Reserved Reserved Reserved Reserved IVEE[0] ICUT1[0] ICUT[30] 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 CLASSIFICATION REGISTERS 2CH 2DH 2EH 2FH Port 1 Class Port 2 Class Port 3 Class Port 4 Class RO RO RO RO 1 2 3 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000,0000 0000,0000 0000,0000 0000,0000 CURRENT REGISTER 30H 31H 32H 33H 34H 35H 36H 37H Current Port 1 (MSB) Current Port 1 (LSB) Current Port 2 (MSB) Current Port 2 (LSB) Current Port 3 (MSB) Current Port 3 (LSB) Current Port 4 (MSB) Current Port 4 (LSB) RO RO RO RO RO RO RO RO 1 1 2 2 3 3 4 4 IPD1[8] Reserved IPD2[8] Reserved IPD3[8] Reserved IPD4[8] Reserved IPD1[7] Reserved IPD2[7] Reserved IPD3[7] Reserved IPD4[7] Reserved IPD1[6] Reserved IPD2[6] Reserved IPD3[6] Reserved IPD4[6] Reserved IPD1[5] Reserved IPD2[5] Reserved IPD3[5] Reserved IPD4[5] Reserved IPD1[4] Reserved IPD2[4] Reserved IPD3[4] Reserved IPD4[4] Reserved IPD1[3] Reserved IPD2[3] Reserved IPD3[3] Reserved IPD4[3] Reserved IPD1[2] Reserved IPD2[2] Reserved IPD3[2] Reserved IPD4[2] Reserved IPD1[1] IPD1[0] IPD2[1] IPD2[0] IPD3[1] IPD3[0] IPD4[1] IPD4[0] 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 *UV and UVLO bits of VEE and VDD asserted depends on the order VEE and VDD supplies are brought up. A = AUTO pin state before reset. M = MIDSPAN state before reset. A3..0 = ADDRESS input states before reset. ______________________________________________________________________________________ 43 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Applications Information RJ-45 CONNECTOR 1 3 PHY RD1+ RD1RX1+ RX124 22 1 2 3 6 -48VOUT 0.1F RXT1 23 75 1000pF 250VAC 75 75 75 0.1F 4 5 0.1F TXCT1 20 0.1F 7 8 1/2 OF 21 H2005A TX1+ 4 TD1+* 19 TX15 TD1- -48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V, (REF TO DGND) 3k 180 VDD VDD AGND A0 A1 A2 A3 RESET 1k HPCL063L VCCRTN 3k INT SDAOUT INTERNAL 50k PULLUP 4.7k SERIAL INTERFACE OPTIONAL BUFFER 180 3k SDAIN AUTO MIDSPAN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V SDA OPTIONAL BUFFER 180 HPCL063L MAX5952 OSC_IN 3k SCL HPCL063L SHD_ OFF ON SCL OPTIONAL BUFFER DGND VEE 0.5 1% SENSE_ GATE_ OUT_ DET_ 1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT 100 1N4448 -48V 1N4002 FDT3612 100V, 120m SOT-223 *USE HALO TG111-HRPE40NY OR PULSE HX6015NL FOR HIGH POWER 1 OF 4 CHANNELS Figure 13. PoE System Block Diagram 44 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 RJ-45 CONNECTOR 1 2 DATA 3 6 4 5 7 -48VOUT 8 -48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V (REF TO DGND) 3k 180 VDD VDD AGND A0 A1 A2 A3 RESET 1k HPCL063L VCCRTN 3k INT SDAOUT INTERNAL 50k PULLUP 4.7k SERIAL INTERFACE OPTIONAL BUFFER 180 3k SDAIN AUTO MIDSPAN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V SDA OPTIONAL BUFFER 180 HPCL063L MAX5952 OSC_IN 3k SCL HPCL063L SHD_ OFF ON SCL OPTIONAL BUFFER DGND VEE 0.5 1% SENSE_ GATE_ OUT_ DET_ 1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT 100 1N4448 -48V 1N4002 FDT3612 100V, 120m SOT-223 1 OF 4 CHANNELS Figure 14. PoE System Block Diagram ______________________________________________________________________________________ 45 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 R10 2 R6 1 C3 15nF R5 1k Q4 MMBTA56 DRAIN 1 2 C6 0.47F 100V 3 4 V+ VDD FB SS_SHDN C4 220F Sanyo 6SVPA220MAA L1 68H, DO3308P-683 D1 DIODES INC.: B1100 R1 2.61k +3.3V +3.3V 300mA C5 4.7F GND GND Q2 MMBTA56 GND MAX5020 VCC NDRV GND CS 8 7 6 5 R8 30 GATE SOURCE Q1 Si2328 DS C9 4.7nF C7 0.22F Q3 MMBTA56 C2 0.022F -48V -48V C1 0.1F C8 2.2F R4 1 R9 1 R2 6.81k R7 1.02k R3 2.61k Figure 15. -48V to +3.3V (300mA) Boost Converter Solution for VDIG 1700 (mils) 1700 (mils) 1700 (mils) 965 (mils) 965 (mils) Figure 16. Layout Example for Boost Converter Solution for VDIG 46 ______________________________________________________________________________________ 965 (mils) High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Component List for VDIG Supply DESIGNATION C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 DESCRIPTION 0.1F, 25V ceramic capacitor 0.022F, 25V ceramic capacitor 15nF, 25V ceramic capacitor 220F capacitor Sanyo 6SVPA220MAA 4.7F, 16V ceramic capacitor 0.47F, 100V ceramic capacitor 0.22F, 16V ceramic capacitor 2.2F, 16V ceramic capacitor 4.7nF, 16V ceramic capacitor B1100 100V Schottky diode 68H inductor Coilcraft DO3308P-683 or equivalent Q2, Q3, Q4 R1, R3 R2 R4, R6, R9 R5 R7 R8 R10 U1 DESIGNATION Q1 DESCRIPTION Si2328DS Vishay n-channel MOSFET, SOT23 MMBTA56 small-signal PNP 2.61k 1% resistors 6.81k 1% resistor 1 1% resistors 1k 1% resistor 1.02k 1% resistor 30 1% resistor 2 1% resistor High-voltage PWM IC MAX5020ESA (8-pin SO) Pin Configuration TOP VIEW RESET 1 MIDSPAN 2 Selector Guide PART SENSE RESISTOR () 0.5 0.5 VDD (V) 3.3 5 MAX5952A_ MAX5952C_ + 36 OSC 35 AUTO 34 OUT1 33 GATE1 32 SENSE1 INT 3 SCL SDAOUT SDAIN A3 A2 A1 4 5 6 7 8 9 MAX5952 31 OUT2 30 GATE2 29 SENSE2 28 VEE 27 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND 20 SHD4 19 SHD3 A0 10 DET1 11 DET2 12 DET3 13 DET4 14 DGND 15 VDD 16 SHD1 17 SHD2 18 SSOP ______________________________________________________________________________________ 47 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Circuits -48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD -48V RTN OUTPUT TO PORT VDD AGND A0 A1 A2 A3 1k 3k VCCRTN SDAOUT OPTIONAL BUFFER 3k RESET INTERNAL 50k PULLUP INT AUTO SDAIN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) N.C. 4.7k SERIAL INTERFACE HPCL063L 180 SDA OPTIONAL BUFFER 180 HPCL063L MAX5952 MIDSPAN OSC_IN 3k SCL HPCL063L SHD_ OFF ON SCL OPTIONAL BUFFER DGND VEE 0.5 1% SENSE_ GATE_ OUT_ DET_ 1N4448 -48V OUTPUT TO PORT 100 -48V FDT3612 100V, 120m SOT-223 NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN VEE AND (AGND + 4V). 1 OF 4 CHANNELS CAN BE UP TO 100k Typical Operating Circuit 1 (without AC Load Removal Detection) 48 ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Typical Operating Circuits (continued) -48V RTN OUTPUT TO PORT -48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD VDD AGND A0 A1 A2 A3 RESET 1k HPCL063L VCCRTN 3k INT SDAOUT INTERNAL 50k PULLUP 4.7k SERIAL INTERFACE OPTIONAL BUFFER 180 3k SDAIN AUTO MIDSPAN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V SDA OPTIONAL BUFFER 180 HPCL063L MAX5952 OSC_IN 3k SCL HPCL063L SHD_ OFF ON SCL OPTIONAL BUFFER DGND VEE 0.5 1% SENSE_ GATE_ OUT_ DET_ 1k 0.47F 100V -48V OUTPUT TO PORT 100 1N4448 -48V 1N4002 FDT3612 100V, 120m SOT-223 CAN BE UP TO 100k 1 OF 4 CHANNELS NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND MUST BE CONNECTED DIRECTLY TO AGND FOR AC DISCONNECT DETECTION CIRCUIT TO OPERATE. Typical Operating Circuit 2 (with AC Load Removal Detection) Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 49 High-Power, Quad, PSE Controller for Power-Over-Ethernet MAX5952 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) SSOP.EPS REV. 36 INCHES DIM A A1 B C e E H L D MAX MIN 0.104 0.096 0.004 0.011 0.017 0.012 0.013 0.009 0.0315 BSC 0.299 0.291 0.398 0.414 0.040 0.020 0.598 0.612 MILLIMETERS MAX MIN 2.65 2.44 0.29 0.10 0.44 0.30 0.23 0.32 0.80 BSC 7.40 7.60 10.11 10.51 0.51 15.20 1.02 15.55 E H 1 TOP VIEW D A1 e A C 0-8 B L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH APPROVAL DOCUMENT CONTROL NO. 21-0040 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 50 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. |
Price & Availability of MAX5952CEAX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |